1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor array substrate.
2. Description of the Related Art
Recently, liquid crystal panels have widely been used in monitor screens of portable personal computers or desk-top personal computers and in project type monitor screens. Particularly, active matrix type liquid crystal panels comprising display pixels each provided with a thin film transistor (hereinafter called a TFT), which serves as a switch for an image signal, are excellent in picture quality such as a contrast or response speed, and widely used.
However, the liquid crystal display panel using TFT has a problem in that the display quality is lowered due to a display potential change called a feedthrough distributed on the display screen, the feedthrough being ascribable to a parasitic capacity of the transistor. Particularly, the distribution of the feedthrough on the display screen tends to become larger in a large size panel, causing a serious problem in the recent tendency to enlarge the screen size.
The feedthrough phenomenon will next be described. Generally, in an active matrix liquid crystal display which uses thin film transistors, the electric potential of the pixel capacity varies at the fall time of a gate write signal due to the parasitic capacity effect between gate source of the thin film transistor. This variation is called a feedthrough voltage. The feedthrough voltage V.sub.FD is given by equation (1) when it is expressed by using a TFT capacity C.sub.GS between the gate source, a liquid crystal capacity C.sub.LC, a storage capacity C.sub.SC and a gate pulse amplitude .DELTA.V.sub.G. EQU V.sub.FD =(C.sub.GS .multidot..DELTA.V.sub.G)/C.sub.LC +C.sub.SC +C.sub.GS( 1)
V.sub.FD : feedthrough voltage, PA1 C.sub.GS : capacity between the TFT gateusource, PA1 C.sub.LC : liquid crystal capacity, PA1 C.sub.SC : storage capacity, PA1 .DELTA.V.sub.G : gate pulse amplitude. PA1 (time elapsed until TFT cut-off voltage),
Next, a description will be made with reference to the feedthrough voltage distributed in the array surface.
Equation (1) gives a gate signal, with ideal pulse, however in a actual active matrix LCD a rounding is developed on a gate write signal (scanning line selection pulse) inputted in the form of square pulse, as the distance from the input point increases due to the time constant, which causes a time difference generated during the time period from the start of the gate signal fall time until the time at which the transistor is turned completely off. Consequently the electric potential of the pixel capacity which is likely to vary due to the feedthrough is restored to some extent, and hence a difference is generated in the feedthrough voltage between the input side with a small rounding of the gate pulse and the non-input side with a large rounding of the gate pulse.
By calculating the rounding effect of the gate pulse, the feedthrough voltage V.sub.FD is expressed by equation (2). EQU V.sub.FD2 =(C.sub.GS .multidot..DELTA.V.sub.G +.intg.I.sub.DS .DELTA.t)/(C.sub.LC +C.sub.SC +C.sub.GS) (2)
.DELTA.t: gate delay time due to the rounding of a pulse
I.sub.DS : TFT mean current which flows for recharging within the above delay time.
Since .DELTA.t is proportional to the wiring time constant (wiring resistance.times.wiring capacity), .DELTA.t is negligibly small on the gate pulse input side and I.sub.DS .DELTA.t .apprxeq.0. Therefore, the feedthrough voltage difference between the gate pulse input side and the opposite side is given by equation (3) as the difference of equation (2) and equation (1). EQU .DELTA.V.sub.FD =(.intg.I.sub.DS .DELTA.t)/(C.sub.LC +C.sub.SC +C.sub.GS)(3 )
As described above, since the differences of the feedthrough voltage in a display screen ascribable to the rounding of the gate signal waveform is proportional to the wiring time constant, the problem becomes larger as an LCD becomes larger.
In order to above the problem as mentioned above, as a method for reducing the distribution of the feedthrough voltage in the display screen, a method, in which the value of (C.sub.LC +C.sub.SC +C.sub.GS) of equation (3) is made larger as much as possible, may be selected; however, an increase in wiring delay and lowering of opening ratio may also course the deteriration of the quality of LCD.
As an applicable method other than the above, there is a method in which the variation of the feedthrough voltage due to the rounding of the gate signal can be compensated by varying an auxiliary capacity of the transistor element in the display screen, the variation being made in the direction of the wiring. An example of this method is described with reference to FIG. 1 (refer to Japanese Patent Laid-open No. 232509/93).
In FIG. 1, numeral 5 denotes a gate signal line, 6 pixel electrode, 8 drain signal line, 12 interlayer insulation layer, 15, 16 and 17 storage capacity, 21 gate electrode, 22 drain electrode and 23 source electrode. In the prior art shown in FIG. 1, the storage capacity C.sub.SC of equation (2) is made larger toward the input side of gate signal and smaller as being spaced apart from the input side. Thus, the feedthrough voltage of the input side V.sub.FD.sup.IN can be made smaller and that of the non-input side V.sub.FD.sup.OUT largeer, with the result that the .DELTA.V.sub.FD becomes OV.
However, the method shown in FIG. 1 is based on a single exposure on the display surface, and hence this method is difficult to apply to a large-sized panel, in which a large number of exposures are applied to prepare the display surface
Now, a system of exposure processes for forming a pattern for a large-sized thin film transistor array substrate will be described. As exposure systems, there are two kinds of systems, one is a full exposure system (a full aligner system) and the other one is a stepping exposure system (a stepping aligner system). In the full exposure system, a product pattern is exposed through a mask of a large size which is equal to or larger than the screen size. With this system, since the screen to be exposed is limited in size by the size of an optical device and the mask, the exposure of a panel of excessibly large size cannot be effected.
On the other hand, in the stepping exposure system, exposure is effected by using a small mask and dividing the whole area of pattern into a number of sections. Particularly, in the case of a display which is formed from array patterns of the same element, any large display can be formed by performing the exposure process repeatedly using the same mask.
However, if the method disclosed in the aforesaid Japanese Patent Laid-open No. 232509/93 is applied to the stepping exposure process, each of the divided data differs from each other and hence masks must be separately provided for each exposure. An example is shown in FIG. 2.
According to FIG. 2, overlap portion 7 of gate signal line 5 and pixel electrode 6 on the thin film transistor array is made smaller in area stepwise as it is spaced apart from the side of the gate signal input. If the portions 7 are formed by the stepping exposure system, in which the product pattern is transversely divided into four sections, the exposure areas (1), (2), (3), (4) are formed in the manner as described above, and hence different masks must be prepared so as to correspond to each of the areas.
However, in this case, the prolonged exposure time caused by the increased number of the mask, complicated accuracy control of the mask connecting work and the mask/electrode overlapping work, and moreover, suspension of exposure work due to the need to prepare excessive number of masks have remarkably lowered the productivity of the system.